Notice Board :

Call for Paper
Vol. 12 Issue 12

Submission Start Date:
December 01, 2020

Acceptence Notification Start:
December 10, 2020

Submission End:
December 20, 2020

Final MenuScript Due:
December 22, 2020

Publication Date:
December 25, 2020
                         Notice Board: Call for PaperVol. 12 Issue 12      Submission Start Date: December 01, 2020      Acceptence Notification Start: December 10, 2020      Submission End: December 20, 2020      Final MenuScript Due: December 22, 2020      Publication Date: December 25, 2020




Volume XI Issue XII

Author Name
Nalini Dhuware, Prof. Anshuj Jain
Year Of Publication
2019
Volume and Issue
Volume 11 Issue 12
Abstract
In this paper Performance in Multi source Wavelet Transform based Secure Image System is the synthesis of multi source image information which is retrieved from the different sensors. It can synthesis the two or more images into one image which is more accurate, all-around and reliable. It can result in less data size, more efficient target detection, and target identification and situation estimation for observers. Also it can make the images more suitable for the task of the computer vision and the follow-up image processing. Various techniques of Multi-focus image fusion and still researchers in the area are introducing new algorithms for improved results. Different parameters like PSNR, MSER and IQI can be used to evaluate the performance of these algorithms.
PaperID
2019/EUSRM/12/2019/57226

Author Name
Sumit Jain, Prof. Aman Saraf
Year Of Publication
2019
Volume and Issue
Volume 11 Issue 12
Abstract
LCD Power Management on High Speed Buffer Amplifier for LCD panel driving system is presented. The proposed architecture has self biased RAIL TO RAIL complementary differential pair for full input output swing, and class B push-pull output driving stage which is suitable for large and small size liquid crystal display, compensation capacitor and resistance are used to improve the settling time and slew rate of the buffer amplifier by stabilizing phase margin, an experimental prototype is simulated using cadence specter in .35 µm CMOS technology which draws only 8 µm static current and provide a settling time of 2.8 µs and rising and 3 µs during four the act area for the design of the buffer is 49*60 µm With power supply of 3.3 it with stand with 1000 pF load capacitance the power consumption of the amplifier under static condition is 66µW.
PaperID
2019/EUSRM/12/2019/57227